%-------------------------------------------------------------------------
\section{Introduction}
%Modern CMOS integrated circuits have become increasingly powerful thanks to technology improvements. On top of various performance requirements, all IC products have critical demands for failure free operation and lifetime guarantee. However the reliability of a circuit does not benefit from technology advances as much as performance. Certain improvements such as scaling down even increase power density and temperature, and result in accelerated lifetime failure~\cite{Jing:ISCAEM}.

Electromigration (EM) is one of the key reliability concerns in modern VLSI circuit designs. Electromigration occurs when a surge of current going through metal wires, causing the drift of metal atoms along with the flow of electrons, causing a depletion of the metal upstream and a deposition of metal downstream along the current flow direction. The upstream thinning increases the wire resistance and ultimately results in open-circuit failures; while the downstream deposition may cause short-circuit failure to the nearby metal. Consequently, EM effect slows down the circuit through time, and in the worst case can lead to the eventual loss of one or more connections and an intermittent failure of the entire circuit. As technology scales, EM is aggravated with the ever-decreasing wire width and rising temperature~\cite{Jing:ISCAEM}~\cite{Jing:IEEE99}. 

Power supply network is one of the most vulnerable interconnects among all the on-chip wires, due to two reasons. First, the current flow direction on power supply network does not change as often as that in regular signal interconnects; Second, the current density on power networks is usually significantly higher than that of signal wires. Since high current density and uni-directional current flow are the two major contributors for the EM effect, mitigating the EM damage on power supply networks is one of the critical reliability concerns for IC designers. 

%All above methods help mitigate the EM effect, but none of them repairs the wires to extend lifetime.
%\subsection{Our Contribution}

Electromigration problem has been well recognized and many methods have been proposed to mitigate the EM effects in interconnects~\cite{Jing:microEM, jing:vlsid05, Jing:xuanEM, Jing: DACEM, Jing:IEEE99}. For example, Abella \emph{et al.} proposed a method to switch he power/ground supply wires by off-chip and on-chip switches~\cite{Jing:microEM}. This method mitigate the EM effects on wires that connect off-chip nodes and on-chip nodes, but it does not apply to on-chip wires. The on-chip power network design remain the same, which unfortunately are more vulnerable to EM as discussed earlier. Lienig and Jerke~\cite{jing:vlsid05} summarized a number of useful design rules for preventing EM hazard. Special design rules are employed to relieve local EM in vias and L-shape wires. Xuan proposed an approach by increasing the most vulnerable wire width~\cite{Jing:xuanEM},  resulting in large area overhead. Dasgupta and Karri proposed a technique to mitigate EM by minimizing the maximum switching activity~\cite{Jing:DACEM}. However, this method cannot be widely used in all circuits and has comparatively high system overhead. Other approaches include using copper instead of aluminum, and covering bottom and sides of copper lines with Tantalum liner~\cite{Jing:IEEE99}. Majority of the proposed solutions usually result in large area/performance overhead, and usually become less effective with increased on-chip temperature.

 
In this paper, we propose a circuit-level current compensation method to make the metal wires ``repair" themselves against the EM effect. We also present an efficient algorithm for our EM-aware design, so that it can be integrated into the standard-cell place and route flow. Our mechanism aims to solve the EM reliability problem with low area and performance overhead.  Compared to prior work, the reliability improvement from this work does not diminish as temperature increases. To the best of our knowledge, the proposed work represents the first design methodology for self-healing EM for power supply network design.  
